CD4502 consists of six inverter/buffers with 3 state outputs. A logic 1 on the OUTPUT DISABLE input produces a high impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic 1 on the INHIBIT input switches all six outputs to logic 0 if the OUTPUT DISABLE input is a logic 0. This device is capable of driving two standard TTL loads, which is equivalent to six times the JEDEC B series IOL standard.
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This product was added to our catalog on Monday 01 May, 2006.
